Design of a High speed and Low Complexity Divider/Squar-root Architecture on a FPGA

Asadi, Yousef and Javidan, Javad and Zare Fatin, Gholamreza and Nooshyar, Mehdi (2017) Design of a High speed and Low Complexity Divider/Squar-root Architecture on a FPGA. Masters thesis, University of Mohaghegh Ardabili.

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Text (طراحی یک تقسیم کننده/ جذر گیر با سرعت بالا و پیچیده گی کم بر روی FPGA) yousef Asadi.pdf Download (445kB) | Preview

Abstract

The floating point division operation is one of the most complex computational operations while it has low speed and a relatively high occupancy. Improving one of lose parameters (speed, area) can be of great help in calculating and implementing algorithms on hardware. Floating point accounting operations are used a many computing computations. its wide range and the scale change of its range allow the designers to implement more precisely the algorithm. although it's difficult to implement an arithmetic. Field Programmable Gate Array are rival main computing machines with High performance and even highly advanced computers use Field Programmable Gate Array to perform complex commands that can be parallelized. Contrary to the progress made and the various implementation strategies, required area and computational calculation especially when the size increases is their main challenge. Therefore, part of this research has been done with the goal of offering smaller, high-performance architectures for floating-point accounting operations for double precision and high precision, which can be implemented in the Field Programmable Gate Array are.

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